At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Key Responsibilities Responsible for scheduling, designing, developing, and supporting IP models of system level memory such
Company: Qualcomm China Job Area:Engineering Group, Engineering Group Software Engineering General Summary: The candidate will work with a fast-paced automotive systems team working on Snapdragon SoCs for leading car OEMs for digital cockpit and ADAS/AV solutions.
We are now looking for an ASIC Top Floorplan Design Engineer. NVIDIA is seeking a talented ASIC Floorplan Engineer to design and implement the world’s leading SoCs and GPUs. This position offers you a unique opportunity
NVIDIA MMPLEX team, located in Shanghai, consists of over 300 team members. We are dedicated to delivering cutting-edge IP solutions to various NVIDIA product lines, including datacenter, GeForce, automotive, networking, and more. Our IPs encompass a
NVIDIA NVLink Fusion delivers industry-leading AI scale-up and scale-out performance with NVIDIA technology plus semi-custom ASICs or CPUs . NVIDIA is seeking a Senior Custom SOC/IP Verification Engineer to verify the next generation NVLink Fusion semi-custom