The NVIDIA GPU clocks group is looking for an excellent Senior ASIC Design Engineer to join the team. The Team is responsible for crafting all aspects of GPU clocking. We collaborate with the frontend design team to
We are now looking for Fullchip Verification Enginneer for the Networking Switch Chip Design Group. As a Engineer at NVIDIAs Networking Chip Design Group, youll join a group of passionate engineers to deliver the next generation
We are now looking for an ASIC Top Floorplan Design Engineer. NVIDIA is seeking a talented ASIC Floorplan Engineer to design and implement the world’s leading SoCs and GPUs. This position offers you a unique opportunity to craft
As chip sizes continue to grow, power efficiency has become critical across all NVIDIA products - from data centers to automotive and personal computing. Our PMU IP, developed over the past 17 years, is essential in
We are now looking for Chip Design Engineer for the Switch Silicon group. As a Chip Design Engineer at NVIDIAs Networking business unit, youll join a group of passionate engineers to design and implement the next
As chip sizes continue to grow, power efficiency has become critical across all NVIDIA products - from data centers to automotive and personal computing. Our PMU IP, developed over the past 17 years, is crucial in
ASIC验证实习生 北京 校招 实习 芯片类 职位描述 1. 参与多媒体NPU IP 模块级/子系统/系统级的全流程验证；2. 根据设计规格制定验证计划，根据设计及架构需求提取验证特性；3. 搭建验证环境，创建并调试验证用例，收集并分析覆盖率；4. 脚本开发，回归等日常验证任务； 职位要求 1. 工科或理科专业在职学生，电子/通信/计算机/自动化等专业加分；2. 可以实习至少6个月以上；3. 有编程经验，至少熟悉一门编程语言(c/c++/python/java/matlab/systemverilog/verilog);4. 具备较强的自学能力和团队协作精神 投递...
Company: Qualcomm China Job Area:Engineering Group, Engineering Group ASICS Engineering General Summary: Requirements: Familiar with ASIC development, especially logic design, RTL coding, verification, synthesis, timing closure and physical design flow Familiarity with Ethernet switching concepts, such as: L2/L3
Company: Qualcomm China Job Area:Engineering Group, Engineering Group ASICS Engineering General Summary: Requirements: Familiar with ASIC development, especially ASIC verification using System Verilog / UVM, SVA and Coverage-driven methodology, Emulation / FPGA validation Familiarity with Ethernet switching concepts, such
By submitting your resume, you’re expressing interest in one of our 2027 Hardware ASIC Engineer New College Grad roles. We’ll review resumes on an ongoing basis, and a recruiter may reach out if your experience fits one
系统工程师（上海） 上海 全职 生产 / 制造 / 加工 - 电子 / 电器 / 半导体 / 仪器 / 仪表 职位描述 岗位职责： 1、跨职能部门工作，在开发全流程不同阶段参与项目需求分析与整理，参与系统/子系统设计，并负责系统方案的设计与文档输出，完成系统规格的定义； 2、对产品规格需求进行软件、硬件、ASIC、结构等的分解,建立系统的体系结构,确定系统各元素之间的接口； 3、做好关键环节把关与协调，配合团队攻关； 4、协助制定产品开发计划,集成及验证方案,对产品开发过程进行检视及技术评审以确保产品需求和规格得到正确实施； 5、及时了解和分析市场、产业动态和竞争对手,视野开阔,对业务有全面理解,可把握产品技术的发展方向和趋势,并结合公司市场产品战略,协助制定产品线路标规划和关键技术实现方式； 6、推广系统工程的新方法/流程/工具/规范 职位要求 1、电子、计算机、通信、机电、自动化、物理类专业本科或者硕士毕业，3年以上相关专业工作经验； 2、掌握一定的系统工程理论以及建模、设计、仿真工具更佳； 3、熟悉Android/Linux系统架构和嵌入式系统开发流程，有过完整的产品系统开发经历，包括需求分析、方案设计、系统实现、试产以及量产和售后服务全流程的经验，理解产品集成、验证、测试过程，并掌握一定的方法； 4、视野开阔,有较广的相关领域知识,对不同领域产品技术均有一定的理解； 5、具备良好的系统工程素养,能够以系统性思维来分析解决问题; 6、具备扎实的动手能力; 7、具有良好的团队合作精神; 8、具备良好的英文阅读和沟通能力； 9、具备良好的文档写作和汇报总结能力； 10、可以胜任重复性或者多样化工作，细致认真，有耐心，责任感强
Job Details: Job Description: Role Overview We are seeking a highly experienced AI Technical Leader to drive the design and deployment of next-generation agentic AI systems optimized for FPGA/ASIC platforms. This role sits at the convergence of:
Monolithic Power Systems, Inc. (MPS) is one of the fastest growing companies in the Semiconductor industry. We are worldwide technical leaders in Integrated Power Semiconductors and Systems Power delivery architectures. At MPS, we cultivate creativity, are
ASIC-PD team is hiring both junior and senior engineers, whose work scope is physical design from RTL to GSDII: design quality check, synthesis, formal check, partitioning, constraint (for both design and process), async check, timing analysis/fixing/signoff, also
SummaryThe people here at Apple dont just build products - they build the kind of wonder thats revolutionized entire industries. Its the diversity of those people and their ideas that encourages the innovation that runs through
With us You do WORK THAT MATTERS We are the most trusted partner imaging the unknown by creating foresight capabilities quicker to discover and prevent threats. Our solutions contribute to the improvement of people’s health and
With us You do WORK THAT MATTERS We are the most trusted partner imaging the unknown by creating foresight capabilities quicker to discover and prevent threats. Our solutions contribute to the improvement of people’s health and
With us You do WORK THAT MATTERS We are the most trusted partner imaging the unknown by creating foresight capabilities quicker to discover and prevent threats. Our solutions contribute to the improvement of people’s health and
RDMANIC架构师 北京、上海、杭州、中国香港 全职 互联网 / 电子 / 网游 - 研发 职位描述 1、关注RDMA NIC、SmartNIC/DPU、RoCEv2、InfiniBand及GPU Direct通信技术,判断AI集群网络对吞吐、时延、扩展性和可靠性的演进需求;2、定义NIC端到端产品架构,包括PCIe主机接口、DMA与地址转换、收发数据通路、队列与完成机制、RDMA传输、拥塞控制、虚拟化、安全隔离和可观测性;3、建立面向训练、推理和存储负载的性能模型,量化带宽、时延、队列、缓存及PPA约束,识别跨主机、芯片和网络的系统瓶颈;4、驱动架构规格和验证方案落地,协同ASIC、固件、驱动、操作系统及AI通信软件,完成前后仿真、芯片Bring up和规模化系统调优。 职位要求 1、网络适配器及RDMA协议架构能力:深入理解QP、MR、WQE、CQE、Doorbell和RDMAVerbs,掌握Read/Write/Send、Atomic、Ordering、ACK/Retry、丢包恢复以及PFC、ECN、DCQCN等流控与拥塞控制机制;2、主机互联、DMA与虚拟化能力:熟悉PCIe、DMA Engine、Descripptor、MSI-X、IOMMU、ATS/PASID和SR IOV,能够定义地址转换、内存保护、设备虚拟化、缓存与一致性边界及多租户隔离方案3、芯片微架构与软硬件协同能力:能够划分TX/RX、队列管理、调度、缓存和内存访问等模块,完成性能、面积、功耗权衡;理解固件、Linux RDMA驱动及通信库边界,具备仿真建模和前后硅调试能力。 投递...
RDMA NIC 研发专家 北京、上海、杭州、中国香港 全职 互联网 / 电子 / 网游 - 研发 职位描述 1、在总体架构和产品规格指导下,负责RDMA NIC关键子系统或模决的微架构设计与研发交付,包括TX/RX数据通路、QP与上下文管理、WQE/CQE处理、DMA与地址转换、队列调度及完成机制等;2、负责RoCEv2或InfiniBand相关协议功能的设计实现与问题闭环,包括Read/Write/Send、Atomic、Ordering、ACK/Retry、异常处理以及PFC、ECN、DCQCN等流控与拥塞控制机制;3、开展模块级性能分析与优化,量化带宽、时延、队列深度、缓存利用率及PPA约束,定位并解决数据通路、内存访问和跨接口交互中的性能瓶颈;4、协同验证、固件、驱动、操作系统及系统团队,完成模块验证、子系统集成、芯片Bring-up、问题定位和规模化环境下的性能调优。 职位要求 1、RDMA协议与数据通路研发能力:熟悉QP、MR、WQE、CQE、Doorbell和RDMAVerbs,理解RDMA传输状态、顺序、可靠传输及拥塞控制机制,能够独立承担相关模块设计与周试;2、主机接口、DMA与队列管理能力:熟悉PCIe、DMA Engine、Descriptpr、MSI-X、IOMMU、ATS/PASID或SRIOV中的一种或多种技术,具备地址转换、内存保护、队列调度或虚拟化模块研发经验;3、ASIC实现与软硬件协同能力:具备模块微架构、RTL实现、架构验证或性能建模能力,能够完成时序、面积和功耗权衡;熟悉固件或Linux RDMA驱动接口,具备前后硅问题定位经验。关键经历学历背景:微电子、电子工程、计算机、通信等相关专业,具备数字电路、计算机体系结构、操作系统和网络基础;岗位经历:具备5年以上NIC、SmartNIC、DPU、RDMA或高性能网络芯片研发经历,独立承担过协议处理、队列管理、DMA、主机接口或收发数据通路中的一个或多个关键模块成功经验:参与过至少一款网络适配器或高性能网络芯片从现格、设计验证到流片、Bring-up的研发过程,并完成国所负责模块的性能或可靠性问题闭环。 投递...