感知算法工程师深圳社招全职互联网 / 电子 / 网游职位描述1.负责扫地机/割草机感知模型的开发,包括视觉障碍物检测、Lidar障碍物检测、前融合模型、深度提取模型等2.负责感知模型的选型、训练优化、评测、数据工程等诸多环不节的落地,持续提效提质3.负责相关模型量产交付过程中badcase定位、修复、验证和发版送代职位要求1.在计算机视觉和深度学习方向有扎实的基础,熟悉2D/3D目标检测常见深度学习模型,有相关项目经验者优先2.熟练掌握Pytorch、TensorFlow、Caffe等深度学习平台,3.具备扎实的C/C++基础,熟悉Shell/Python/Perl等某一种脚本语言;4.具有优秀的分析能力与解决问题的能力,具有良好的沟通能力;5.快速的学习能力和清晰的逻辑思维能力;6.具有自动驾驶、机器人、扫地机、割草机行业量产经验优先7. 基于camera/Lidar做过通用障碍物检测并有落地经验,熟悉线激光/dtof优先;投递...
Design, implement and maintain the software components Build and test the software components Qualifications Qualifications MS Computer Science, Electronics Engineering or related discipline Strong command of python Strong analytical and problem solving skills Result oriented, positive attitude
General Information Job Title Validation / Verification Eng, Staff Engineer Job ID 17036 Country China City Shanghai Date Posted 17-Apr-2026 Job Category Engineering Job Subcategory Validation / Verification Eng Hire Type Employee Remote Eligible No Descriptions
【2026】芯片中后端实现工程师上海校招正式互联网 / 电子 / 网游职位描述1.参与RTL2GDS全流程设计交付，包括逻辑综合，PPA优化，芯片物理实现，流片签核等2. 芯片PPA优化和方法学研究3. 完成芯片顶层，子系统，模块级别的SDC集成和质量检查4. 完成形式验证分析，保证代码功能一致性5. 完成低功耗设计实现与验证，模块和顶层UPF交付6. 芯片物理验证和签核7. 完成静态时序分析与时序收敛8. 负责芯片功耗分析，IREM分析与签核9. 负责芯片中后端设计自动化流程的搭建和维护职位要求1. 微电子、电子工程，计算机，通信工程专业相关硕士及以上应届毕业生2. 熟悉数字集成电路设计和静态时序分析的基本原理，熟练掌握verilog编写3. 熟悉linux开发环境，熟悉tcl、perl、python等脚本语言（一门或以上)4. 学习能力强，工作积极投入，具有良好的逻辑思维和独立分析问题的能力5. 富有事业心和团队合作精神，良好的中英文听说读写能力6. 有芯片设计各环节相关的实习或项目经验为加分项投递...
【2026】芯片DFT设计工程师上海校招正式互联网 / 电子 / 网游职位描述1.参与制定完整的SOC芯片DFT方案；2.完成DFT电路设计的实现与验证，包括Scan、Mbist、Bscan、ATPG和测试向量生成等；3.完成DFT模式的时序约束，协助P&R完成DFT STA/Power Signoff；4.配合测试和产品部门进行CP/FT测试程序的开发调试和故障诊断，良率提升；5.进行DFT流程的研究和优化，以及维护和优化自动化设计平台；职位要求1.微电子、电子工程，计算机，通信工程专业相关硕士及以上应届毕业生；2.熟悉Verilog语言，熟悉芯片设计流程；3.熟悉DFT相关知识，包括MBIST, BSCAN, SCAN, JTAG等；4.熟悉 Synopsys / Mentor 等可测性设计工具；5.能够熟练使用 Perl（Python）、Tcl 和 Shell 脚本优先；6.学习能力强，具备良好的沟通能力和团队合作能力，具有认真负责的工作态度。投递...
Introduction to the job ASML Customer Support (CS) Diagnostics is at the core of ASML’s ambition to significantly reduce diagnostic labor hours, improve system availability, and enable predictive and self‑healing service capabilities towards 2030. The Data
Company Description Join a multibillion-dollar global company that brings together amazing technology, people, and operational scale to become a powerhouse in the memory industry. Headquartered in Rancho Cordova, California, Solidigm combines elements of an established, successful
Company Description Join a multibillion-dollar global company that brings together amazing technology, people, and operational scale to become a powerhouse in the memory industry. Headquartered in Rancho Cordova, California, Solidigm combines elements of an established, successful
NVIDIA has been transforming computer graphics, PC gaming, and accelerated computing for more than 30 years. It’s a unique legacy of innovation that’s fueled by great technology—and amazing people. Today, we’re tapping into the unlimited potential
We are now looking for a Physical Design Engineer. VLSI Physical Design Team at NVIDIA Shanghai has been built up since 2005. The team has made contribution to various successful products launched by NVIDIA Corporation over
【27届暑期】数字IC综合实现实习生上海实习研发 - 电子 / 半导体职位描述1. 逻辑综合与优化： 使用Synopsys DC/FC或Cadence Genus等工具，进行模块级/芯片级综合，制定并实施综合策略，优化时序、面积和功耗。2. 静态时序分析（STA）： 使用PrimeTime等工具，进行全芯片的签核级时序验证，分析建立时间、保持时间，并能熟练处理时钟域交叉（CDC）问题。3. 形式验证： 使用Formality或Conformal等工具，完成RTL与门级网表之间的逻辑等效性验证（LEC），确保功能一致性。4. 设计约束（SDC）编写与管理： 制定准确、完备的时序约束文件，指导综合与STA流程。5. 与前后端团队协作： 与前端设计工程师/DFT工程师紧密合作，理解设计意图并提出可综合性建议；与后端物理设计工程师协作，解决时序收敛等关键问题。职位要求1. 微电子、集成电路、电子工程、计算机科学等相关专业，硕士以上学历。2. 扎实的数字电路知识基础，深入理解CMOS原理、时序分析理论（建立/保持时间、时钟抖动、偏斜等）和低功耗设计方法学。3. 熟悉Verilog或SystemVerilog等数字电路设计语言。4. 熟悉Linux操作环境及基本的脚本语言（Tcl/Perl/Python/Shell之一）。5. 了解数字IC前端到后端的完整设计流程，特别是中端的关键步骤。6. 具备出色的分析问题、解决问题的能力，严谨细致，具备良好的团队沟通与协作精神。优先条件（符合以下条件者优先考虑）：1. 有基于业界主流工艺节点（如28nm, 12nm, 7nm等）的芯片项目（课设、竞赛、实习）中端或前端实践经验。2. 对UPF等低功耗设计流程有实际项目经验。熟悉AMBA总线协议（AHB、APB、AXI）或常见接口协议（如DDR、PCIe、USB）。3. 在形式验证、逻辑综合或STA方面有深入的研究或项目经验。投递...
Company Description About Grab and Our Workplace Grab is Southeast Asias leading superapp. From getting your favourite meals delivered to helping you manage your finances and getting around town hassle-free, weve got your back with everything.
Every CPU, GPU, and Tegra SoC NVIDIA has shipped in the past four years passed through our toolchain on its way to production. Over 200 product SKUs were optimized during the Blackwell generation alone! Now were
Every day, Global Payments makes it possible for millions of people to move money between buyers and sellers using our payments solutions for credit, debit, prepaid and merchant services. Our worldwide team helps over 3 million
Company: Qualcomm China Job Area:Interns Group, Interns Group Interim Engineering Intern - SW General Summary: Main Responsibilities SW development on Qualcomm Chips. new feature design, technology investigation, system optimization, code developing and cross team co-work. There
NVIDIAs GPUs and Tegra SOCs are the world leaders in performance and efficiency, and we are continually innovating in creative and unique ways to improve our ability to deliver extraordinary solutions in a wide range of
NVIDIA, a world-class technology company, is looking for an exceptional and ambitious individual to join our team as a Product Engineer. This role offers a unique opportunity to be part of a company that has revolutionized
The NVIDIA GPU clocks group is looking for an excellent Senior ASIC Design Engineer to join the team. The Team is responsible for crafting all aspects of GPU clocking. We collaborate with the frontend design team
芯片设计工程师 北京 社招 全职 职位 ID：A16005 职位描述 1. 负责NPU数字电路开发。 2.和算法及系统架构团队合作开发子系统并满足系统设计要求。 3.工作内容包括RTL 设计， FPGA原型验证，支持设计验证和后端设计。 4. 参加样片的功能调试及验证，检验芯片的设计和性能。 职位要求 1. 具有IC或者NPU/GPU/CPU系统设计经验4年以上 2. 掌握DNN/CNN的相关知识及系统应用。 3. 具有很好地使用编程语言（VHDL/Verilog/Systemverilog）进行 RTL代码开发经验。 4. 掌握先进IC开发流程知识，包括电路设计，系统集成，代码验证和后端实现。 5. 熟悉用Verilog/systemVerilog进行RTL代码验证。 6. 熟悉脚本语言，如tcl, perl, python等。 7. 具有良好的EDA工具使用经验。 投递...
NVIDIAs Silicon Co-design Group (SCG) sits at a rare intersection: we own the full product development lifecycle, from early architecture definition through silicon bringup to product release. Our ArchDev team is the hub for silicon and