The NVIDIA GPU clocks group is looking for an excellent Senior ASIC Design Engineer to join the team. The Team is responsible for crafting all aspects of GPU clocking. We collaborate with the frontend design team to understand the
The NVIDIA SOC group is looking for ASIC Design and Verification Interns to join the SysASIC and Clock teams. In this position, you will participate in the design and verification of complex reset/fuse/ism/sysctrl/boot and clock-related logic for latest NVIDIA
Company: Qualcomm China Job Area:Engineering Group, Engineering Group ASICS Engineering General Summary: Requirements: Familiar with ASIC development, especially logic design, RTL coding, verification, synthesis, timing closure and physical design flow Familiarity with Ethernet switching concepts, such as: L2/L3 forwarding, bridging,
We are now looking for Fullchip Verification Enginneer for the Networking Switch Chip Design Group. As a Engineer at NVIDIAs Networking Chip Design Group, youll join a group of passionate engineers to deliver the next generation state of
We are now looking for Chip Design Internships for the Switch Silicon group. As a Chip Design Intern at NVIDIAs Networking business unit, youll join a group of passionate engineers to implement the next generation state of the
NVIDIA has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years. It’s a unique legacy of innovation that’s fueled by great technology—and amazing people. Today, we’re tapping into the unlimited potential
We are now looking for an ASIC Top Floorplan Design Engineer. NVIDIA is seeking a talented ASIC Floorplan Engineer to design and implement the world’s leading SoCs and GPUs. This position offers you a unique opportunity to craft and to
Locations: Shanghai, China Categories: Engineering Req ID: 87910 WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming
As chip sizes continue to grow, power efficiency has become critical across all NVIDIA products - from data centers to automotive and personal computing. Our PMU IP, developed over the past 17 years, is crucial in
ASIC-PD team is hiring both junior and senior engineers, whose work scope is physical design from RTL to GSDII: design quality check, synthesis, formal check, partitioning, constraint (for both design and process), async check, timing analysis/fixing/signoff, also all related flow.
NVIDIAs Silicon Co-Design Group is seeking a Senior Infrastructure Automation Engineer to innovate, develop, and integrate innovative AI solutions into the design and automation infrastructure that powers our chips. Every CPU, GPU, and Tegra SoC NVIDIA has shipped
By submitting your resume, you’re expressing interest in one of our 2027 Hardware ASIC Engineer New College Grad roles. We’ll review resumes on an ongoing basis, and a recruiter may reach out if your experience fits one
NVIDIA has continuously reinvented itself. Our invention of the GPU sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. Today, research in artificial intelligence is booming worldwide, which calls
The NVIDIA System-on-Chip (SOC) design group is looking for a motivated intern to join our Methodology team. In this role, you will help improve the way we design, configure, and verify in SOC Design fields— making them faster, more
As chip sizes continue to grow, power efficiency has become critical across all NVIDIA products - from data centers to automotive and personal computing. Our PMU IP, developed over the past 17 years, is essential in
NVIDIAs GPUs and SOCs are the world leaders in performance and efficiency, and we are continually innovating in creative and unique ways to improve our ability to deliver extraordinary solutions in a wide range of sectors.
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Job Title: Lead Design Engineer Location: Nanjing, China Cadence is a pivotal leader in electronic design, building upon
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Job Description Job Title: Design Design Engineer II Location: Nanjing, China Cadence is a pivotal leader in electronic
Company: Qualcomm China Job Area:Engineering Group, Engineering Group Hardware Applications Engineering General Summary: Job Overview We are looking for a senior ASIC NPI (New Product Introduction) Support Engineer with rich end-to-end chip delivery experience. This role will
Company: Qualcomm China Job Area:Interns Group, Interns Group Interim Engineering Intern - SW General Summary: 1. ASIC IP/SoC design and verification 2. Participate in whole ASIC flow, including development of micro architecture specification, RTL implementation, design verification, synthesis, timing closure,