At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Primary Responsibilities: ○ Supporting pre-silicon integration, usage, and implementation of memory subsystem products ○ Helping with
PLAY, GROW and WIN To be a part of Virtuos means to be a creator. At Virtuos, we harness the latest technologies to make games better and more immersive than ever before. That is why we
Company: Qualcomm China Job Area:Engineering Group, Engineering Group ASICS Engineering General Summary: Requirements: Deep expertise in ASIC development, especially logic design, RTL coding, verification, synthesis, timing closure and physical design flow Deep expertise in Ethernet switch architecture, including:
Making IP video a reality, NDI® moves the world’s content. Network Device Interface (NDI) is a high-performance standard that harnesses the power of Software, Computers, and Networks to make video creation and delivery accessible and easy
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Overview: This role sits at the intersection of deep protocol expertise and direct partnership with our
Company Description Renesas is one of the top global semiconductor companies in the world. We strive to develop a safer, healthier, greener, and smarter world, and our goal is to make every endpoint intelligent by offering
Company Description Renesas is one of the top global semiconductor companies in the world. We strive to develop a safer, healthier, greener, and smarter world, and our goal is to make every endpoint intelligent by offering
We are looking for a GPU C++ Modeling Engineer intern – Performance/Functional Modeling, Validation and Analysis of Shader. TPC arch team is a fast-growing team which welcomes all level engineers to join. Our aim is to
Company: Qualcomm China Job Area:Engineering Group, Engineering Group ASICS Engineering General Summary: Requirements: Familiar with ASIC development, especially logic design, RTL coding, verification, synthesis, timing closure and physical design flow Familiarity with Ethernet switching concepts, such as: L2/L3
Company: Qualcomm China Job Area:Interns Group, Interns Group Interim Engineering Intern - SW General Summary: 1. ASIC IP/SoC design and verification 2. Participate in whole ASIC flow, including development of micro architecture specification, RTL implementation, design verification, synthesis,
ASIC-PD team is hiring both junior and senior engineers, whose work scope is physical design from RTL to GSDII: design quality check, synthesis, formal check, partitioning, constraint (for both design and process), async check, timing analysis/fixing/signoff, also
By submitting your resume, you’re expressing interest in one of our 2027 Hardware ASIC Engineer New College Grad roles. We’ll review resumes on an ongoing basis, and a recruiter may reach out if your experience fits
NVIDIA has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years. It’s a unique legacy of innovation that’s fueled by great technology—and amazing people. Today, we’re tapping into the unlimited potential
The NVIDIA GPU clocks group is looking for excellent Senior Formal Verification engineers to join the team. The Team is responsible for crafting all aspects of GPU clocking. The team collaborates with the frontend design team
By submitting your resume, you’re expressing interest in one of our 2027 GPU Architecture Engineer – New College Grad roles. We’ll review resumes on an ongoing basis, and a recruiter may reach out if your experience
The NVIDIA SOC group is looking for ASIC Design and Verification Interns to join the SysASIC and Clock teams. In this position, you will participate in the design and verification of complex reset/fuse/ism/sysctrl/boot and clock-related logic
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Responsibilities Drive low-power design and verification activities, including UPF modeling, multi-voltage domain design, and power-aware simulation/emulation
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Position Description: Responsible for development and maintenance of the synthesizer for Palladium. Implementation for new VHDL/Verilog feature
Locations: Shanghai, China Categories: Engineering Req ID: 92014 ADVANCE YOUR CAREER. ADVANCE THE WORLD. At AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to
We are now looking for a Power Methodology and Analysis Engineer. NVIDIA prides ourselves in having energy efficient products. We believe that continuing to maintain our products energy efficiency compared to competition is key to our